A typical semiconductor design process includes numerous steps. Initially, a circuit designer prepares a schematic diagram that includes logical connections between logic elements that form an integrated circuit. The schematic diagram is then tested to verify that the logic elements and associated logical connections perform a desired function. Once the circuit is verified, the schematic diagram is converted into a mask layout database that includes a pattern of polygons. The polygons may represent the logic elements and the logical connections contained the schematic diagram. The mask layout database is then converted into multiple photomasks, also know as masks or reticles, that may be used to image different layers of the integrated circuit on to a semiconductor wafer.
Over the past several years, the number of transistors that form an integrated circuit has increased dramatically. Additionally, the operating speed of integrated circuits has also increased. High-speed integrated circuits require a stable voltage, regardless of the input current required. However, spike currents generated during switching can cause power (VCC) and ground (GND) voltage levels to fluctuate, which may cause ringing in the output waveform or a delay in response speed. The spike currents, also known as switching noise, are caused by changes in current through various parasitic inductances. The simultaneous switching of the input/output drivers and internal circuits can increase the voltage drop on the power supply. This power supply noise not only will introduce additional signal delay, but also may cause false switching of logic gates. Typically, decoupling capacitors may be used to reduce the impedance between power and ground, which minimizes the effects of current spikes and board noise on the IC, keeps the power supply within specification, and provides signal integrity for the IC.
The decoupling capacitors may be placed in a mask layout database manually by a layout designer using schematics to determine a location for the capacitors or automatically by a synthesis tool using a netlist associated with the schematics. The selected locations of the decoupling capacitors in the mask layout database, however, may not be optimal and thus, the use of space in the mask layout database may be inefficient. Furthermore, the decoupling capacitors may need to be manually connected to the power and ground signals by the layout designer. During the routing process, the layout designer may need to move polygons in order to provide a connection from the decoupling capacitor to the power supply. The layout designer may inadvertently create design rule violations or connectivity errors. The layout designer may then have to correct the violations and errors until the mask layout database is clean. The process of iteratively correcting the design rule violations may take several hours or even days to complete and can increase the time needed to design the integrated circuit. The additional time required to complete layout may also delay the production of a photomask set used to fabricate the integrated circuit.